MRAM-Based Ising Chip Uses 96,000 Spins to Speed Chip Routing and Layer Assignment

# What this development is Researchers at Beihang University, working with Suzhou Inston Technology and Empyrean Technology, have built a spintronic Ising machine based on CMOS-integrated, voltage-controlled magnetoresistive random-access memory (MRAM). The chip contains 96,000 all-to-all connected spins and supports sub-nanosecond update times per spin. The team applied the device to combinatorial optimisation problems encountered in electronic design automation (EDA), including chip routing and layer assignment.

# Why it matters for chip design Routing and layer assignment in modern integrated circuits are combinatorial problems that grow quickly in complexity as designs scale. Traditional software solvers can be slow or require significant compute resources. A hardware Ising machine maps these optimisation tasks onto coupled spins and seeks low-energy configurations that correspond to good solutions. Using MRAM-based spins offers non-volatility and a path to dense, CMOS-compatible hardware accelerators that update very quickly.

# How the MRAM Ising machine works The system uses voltage-controlled MRAM elements as stochastic or deterministic spins. These spins are connected in an all-to-all topology on the chip to represent pairwise interactions in an Ising Hamiltonian. The chip's sub-nanosecond update capability lets it iterate the spin states quickly, enabling many trials or rapid annealing-like searches for low-energy configurations. Integration with standard CMOS processes makes the approach compatible with existing chip-manufacturing flows.

# Demonstrated applications The reported device was tested on EDA-style problems, specifically routing and layer assignment. Those tasks were formulated as optimisation problems that map onto the Ising model: spins represent routing choices or layer decisions, and coupling weights encode conflict, overlap, or cost constraints. Running the problem on the MRAM Ising hardware produces candidate solutions by converging the spin network toward low-energy states.

# Who built it and how they collaborated Beihang University led the research, collaborating with Suzhou Inston Technology and Empyrean Technology. The MRAM elements and spintronic circuit topology were implemented on a CMOS-integrated chip, combining spintronic device properties with standard semiconductor circuitry for control and readout.

# Performance and implications The notable hardware metrics are the 96,000 spins in an all-to-all connected arrangement and sub-nanosecond per-spin update times. Fast updates increase the number of solution iterations achievable per unit time, which can shorten time-to-solution for hard combinatorial tasks. MRAM's non-volatile character and voltage control also suggest lower static energy and potential for compact accelerator designs that sit alongside digital logic in chip flows.

# Where this fits in the broader landscape This MRAM Ising machine is part of a wider trend exploring spintronics and memristive devices for specialised optimisation and AI hardware. Other groups are developing hybrid approaches that combine memristors, magnetic tunnel junctions, or resistive elements for intrinsic annealing, energy-efficient AI, or on-chip learning. The MRAM-based approach emphasizes CMOS compatibility and focuses on EDA problems relevant to the semiconductor industry.

# Practical next steps for engineers and designers

# Bottom line A CMOS-integrated, voltage-controlled MRAM Ising chip with 96,000 spins and sub-nanosecond updates demonstrates a practical hardware route for accelerating combinatorial problems in chip design, notably routing and layer assignment. The combination of MRAM device properties and fast spin updates makes this a relevant option for EDA hardware acceleration and for compact, specialised optimisation accelerators.